The present invention relates to a mode control circuit provided inside a semiconductor integrated circuit, which mode control circuit controls actions and functions of the semiconductor integrated circuit based on a control signal from outside.
The semiconductor integrated circuit (hereinafter referred to as xe2x80x9cICxe2x80x9d) needs to have an increased number of input/output terminals for higher functionality to be achieved, while meeting requirements for smaller sizes, and is necessarily subjected to a limitation on a pitch of the input/output terminals.
A method of performing the original number of functions with a reduced number of input/output terminals is known. The IC is provided with a control terminals for inputting a signal from outside, and an encoder circuit. By changing the voltage level of the signal supplied from outside a greater number of functions or conditions may be controlled without increasing the number of the control terminals.
In particular, recent years have observed serial control systems for a plurality of conventional functions as well as conditions to be controlled with merely one to three control terminals, such as by changing a voltage level of a control signal input into a control terminal, or by time-sequentially changing pulse intervals. The serial control systems are implemented generally by provision of a mode control circuit in the IC.
FIG. 5 is a circuit diagram of a conventional mode control circuit. In particular, this figure shows a mode control circuit of the type in which functions may be selected by changing a voltage level of a control signal input into a single control terminal. This mode control circuit comprises a first comparator 101 which compares the voltage level of a control signal input into a control terminal 100 and a predetermined threshold voltage V1 and outputs the result of such comparison in the form of a logic level, a second comparator 102 which compares the voltage level of the control signal input into the control terminal 100 and a predetermined threshold voltage V2 and outputs the result of such comparison in the form of a logic level, and an encoder 110 which receives the comparison results in the form of logical levels from the first comparator 101 and the second comparator 102 input thereto to have only one of the three outputs selected as effective.
The encoder 110 is constituted with an inverter 106 which inverts the logic level output by the first comparator 101, an inverter 105 which inverts the logic level output by the second comparator 102, a 2-input NAND gate 107 to which the logic levels output by the first comparator 101 and the second comparator 102 are input. A 2-input NAND gate 108 receives the outputs of the inverter 105 and the inverter 106. A 2-input NAND gate 109 receives the outputs of the inverter 106 and the logic level output by the second comparator 102. The NAND gates 107, 108, and 109 output signals OUT1, OUT2, and OUT3 respectively. In other words, this mode control circuit is adapted to select any of three functions with a single control terminal 100.
FIG. 6 is a circuit diagram of the first comparator 101. The second comparator 102 has the same structure. The first comparator 101 comprises a constant current source 120, a differential pair of PNP transistors TN11 and TN12, a current mirror circuit of NPN transistors TP11 and TP12, a first emitter follower circuit (level shift circuit) made of a resistor R11 and a PNP transistor TN13, a second emitter follower circuit made of a resistor R12 and a PNP transistor TN14, and resistors R13 and R14 for dividing a power supply voltage Vcc to generate the threshold voltage.
In other words, the comparator shown in FIG. 6 serves as a differential amplifier circuit to output at a node OUT a current proportional to a difference between a voltage level at an input terminal IN (which is the same as the control terminal 100) and a predetermined voltage (the threshold voltage) across the two terminals of the resistor R14. Incidentally, the first emitter follower circuit and the second emitter follower circuit are provided to keep the PNP transistors TN11 and TN12 respectively from getting saturated even when a low voltage near a ground potential GND is given to the input terminal IN.
The working of the comparator 101 will be explained here. When the voltage level given to the input terminal IN is lower than a base potential of the PNP transistor TN14, that is, when the voltage level of a control signal input into the control terminal 100 is lower than the threshold voltage of the comparator, then the base potential of the PNP transistor TN11 becomes greater than a base voltage of the PNP transistor TN12 and therefore the current of the constant current source 120 is nearly all conducted to the PNP transistor TN11.
At this time, by a function of the current mirror circuit including the PNP transistors TN11 and TN12, there is a tendency for the PNP transistor TP12 to draw out a current from the PNP transistor TN12 so as to conduct the same current as a current conducted via the PNP transistor TN11 and through the PNP transistor TP11. However, because the current of the constant current source 120 is nearly all conducted to the PNP transistor TN11 as described, the current to be supplied from the PNP transistor TN12 becomes smaller, with a resultant failure to take out a substantial current from the node OUT, so that a low logic level is output from the comparator.
On the contrary, if the voltage level given to the input terminal IN is higher than the base potential of the PNP transistor TN14, that is, when the voltage level of the control signal to be input into the control terminal 100 is higher than the threshold voltage of the comparator, then the base potential of the PNP transistor TN11 becomes smaller than the base potential of the PNP transistor TN12 and therefore the current of the constant current source 120 is almost conducted to the PNP transistor TN12.
In other words, the PNP transistor TN11 fails to have a substantial current conducted therethrough, and by a function of the current mirror circuit including the PNP transistors TN11 and TN12, the PNP transistor TP12 is caused draw out from the PNP transistor TN12 a faint identical current to a current conducted via the PNP transistor TN11 and through the PNP transistor TP11. Therefore, most of the current supplied from the PNP transistor TN12 is taken out of the node OUT, with a result that a high logic level is output from the comparator.
Next, working of the mode control circuit will be explained with an assumption that the threshold voltage V1 of the first comparator 101 to be ⅔ of the power supply voltage Vcc, and the threshold voltage V2 of the second comparator 102 to be ⅓ of the power supply voltage Vcc.
When the voltage level of the control signal is greater than the threshold voltage V1 of the first comparator 101 (i. e. ⅔ Vcc), the first comparator 101 and the second comparator 102 both output a high logic level. Accordingly, in the encoder 110, the NAND gates 108 and 109 output a low logic level and the NAND gate 107 outputs a high logic level. As a consequence, only the signal OUT1 is selected (i.e. output).
When the voltage level of the control signal is lower than the threshold voltage V2 of the second comparator 102 (i. e. ⅓ Vcc), the first comparator 101 and the second comparator 102 both output a low logic level. Accordingly, in the encoder 110, the NAND gates 107 and 109 output a low logic level and the NAND gate 108 outputs a high logic level. As a consequence, only the signal OUT2 is output.
Finally, when the voltage level of the control signal intervenes between the threshold voltage V1 and the threshold voltage V2, the first comparator 101 outputs a low logic level and the second comparator 102 outputs a high logic level. Accordingly, in the encoder 110, the NAND gates 107 and 108 output a low logic level and the NAND gate 109 outputs a high logic level. As a consequence, only the signal OUT3 is output.
In the conventional mode control circuit, it is enough to provide a few control terminals to control a plurality of functions or conditions in the semiconductor integrated circuit. However, this means that there is at least a need to provide dedicated control terminals for inputting the control signals.
It is an object of the present invention to provide a mode control circuit in which there is no need to provide dedicated terminals for inputting control signals. This is realized by provision of signal output terminals which can be also used as the control terminals. Since dedicated control terminals are not provided, the number of input/output terminals in a semiconductor integrated circuit can be reduced.
The mode control circuit of the present invention comprises an encoding unit which makes any of a plurality of signal outputs effective in accordance with a given signal level. Further, a mode control unit changes a potential level to be given to the encoding unit, at a signal output terminal for outputting an internally generated signal generated inside a semiconductor integrated circuit, in accordance with an input of a predetermined current from outside or with an output of a predetermined current from the signal output terminal to outside.
According to the present invention, the mode control unit changes the voltage level changed to be given to the encoder based on a current given from outside to a signal output terminal or suctioned out of the signal output terminal. Thus, the signal output terminal can concurrently serve not simply for outputting a signal generated inside the semiconductor integrated circuit, but also as a control terminal to input a control current.
Further, the mode control unit comprises three transistors, two constant current sources, and two load resistors. Thus, the configuration is simple.
Further, means for implementing the input of the predetermined current to the signal output terminal from outside or the output of the predetermined current from the signal output terminal to outside comprises a load resistor for giving a current from a power supply line to the signal output terminal, a load resistor for suctioning a current from a grounding line and the signal output terminal, and two switches for controlling the respective currents to inflow or outflow. Thus, the configuration is simple.
Further, means for having the signal output terminal outputting predetermined currents therefrom comprises two load resistors for suctioning the currents from the signal output terminal to a grounding line, and two switches for controlling the respective currents to be suctioned. Thus, the configuration is simple.
Further, means for inputting predetermined currents from outside to the signal output terminal comprises two load resistors for giving the currents from a power supply line to the signal output terminal, and two switches for controlling the respective currents to inflow. Thus, the configuration is simple.
Further, the second constant current source can have a current reduced to 1/n (where n is the transistor size of the first transistor when the transistor size of the second transistor is 1) of a current of the first constant current source, and the first and second load resistors are allowed to have increased values to give a signal of a stable potential level to the post-staged the encoding unit, whereby the capacitance of a capacitor C can be reduced.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.